Informatics Publishing Limited

V. Jean Shilpa ¹, P. K. Jawahar ¹

Affiliations
1 Department of Electronics & Communication, B. S. Abdur Rahman University, IN

Abstract

One of the greatest challenges of FPGA is the crave for a platform, which runs a system, handles a software and co-ordinates exchange with peripherals. To explore this advantage on FPGA with energy efficiency, this work aims at developing multithreading on ARM cortex dual core A9 processor present in Zedboard FPGA. To enhance the speed of execution on this processor and to allow concurrency, multithreading is developed using intel thread building blocks(TBB) library which aids in creating task based parallelism on FPGA being the first of its kind. In the first step towards this process, the processor is booted with Ubuntu 12.04 linux operating system making it as a standalone processor. This system is enabled with graphical user interface using xillinux IP library FPGA code kit. To test the efficiency of multihreading on the processing system of Zedboard, an application known as 2D - raytracer is developed using the parallel-for loop scheduling method which aids in running all the iteration loops in the code into chunks and runs each chunk as a separate thread under intel TBB. In this application an image was parallelized by speculating each pixel running in parallel resulting in excellent speedup. The newly implemented multithreading achieves a speedup of 53% compared to sequential execution on the same processor. This method explores the flexibility of parallel processing on FPGA.

Keywords

Dual Cortex A9 ARM(advanced Risc Machines) Processor, Field Programmable Gate Array(FPGA), Intel TBB(Thread Building Blocks), Software Development Kit(SDK), Xilinx Platform Studio(XPS), Zedboard(Zynq Evaluation And Development Board)

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V. Jean Shilpa ¹, P. K. Jawahar ¹, S. Karthik ²

Affiliations
1 Department of ECE, B.S. Abdur Rahman University, Chennai - 600048, Tamil Nadu, IN
2 Department of ECE, SRM University, IN

Abstract

Objectives: A hardware-software co-design of Least Mean Square (LMS) adaptive FIR filter utilized for the real time noise cancellation purpose has been designed and demonstrated. Method/Analysis: This LMS adaptive filter which serves as a better choice in filtering real-time signals with noise, is being designed as an IP for various different users to make the filter reconfigurable to their designs. Fascinating feature about creating an IP on Zedboard which belong to the Zynq series of FPGA boards is to design the LMS filter in Simulink and convert to RTL (Register Transfer Level) logic by employing HDL coder. This process simplifies the task of either writing an HDL code or designing circuits using transistors, which is time-consuming and cumbersome. Findings: To estimate the performance the IP designed is profiled with the Simulink of MATLAB to estimate the functions, which takes more time for execution in the Simulink design of LMS adaptive filter. Profiling the application, it has been found out that LMS algorithm block for the calculation of adaptive coefficients takes around 311.63ns time/call of the execution time. Hence only this block is imported to FPGA as a soft-core block and interconnected with the hardcore ARM cortex A9 processor block which achieves hardware-software co-design of LMS adaptive filter. Application: This method simplifies the process of hardware-software co-design process, which can be applied to any complex design that can be generated from MATLAB/Simulink and generate the same design as an application to run on an advanced FPGA board.

Keywords

Field Programmable Gate Array (FPGA), IP (Intellectual Property), LMS (Least Mean Square) Algorithm, Simulink, ZedBoard (Zynq Evaluation and Development Board).

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